View ATA6020N_1119578.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features/Benefits
* * * * * * * *
Programmable System Clock with Prescaler and Three Different Clock Sources Very Low Sleep Current (< 1 A) Very Low Power Consumption in Active, Power-down and Sleep Mode 2-Kbyte ROM, 256 4-bit RAM 12 Bi-directional I/Os Up to 6 External/Internal Interrupt Sources Synchronous Serial Interface (2-wire, 3-wire) Multifunction Timer/Counter with - Watchdog, POR and Brown-out Function - Voltage Monitoring Inclusive Lo_BAT Detection - Flash Controller ATAM893 Available (SSO20) - Code-efficient Instruction Set - High-level Language Programming with qFORTH Compiler
Description
The ATA6020N is a member of Atmel's 4-bit single-chip microcontroller family. It contains ROM, RAM, parallel I/O por ts, one 8-bit programmable multifunction timer/counter with modulator function, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with external clock input and integrated RC-oscillators. Figure 1. Block Diagram
VSS VDD OSC1
Low-current Microcontroller for Watchdog Function ATA6020N
Brown-out protect RESET Voltage monitor External input VMI
RC oscillators
External clock input UTCM Timer 1 interval- and watchdog timer
Clock management
ROM
2 K x 8 bit
RAM
256 x 4 bit
Timer 2 8/12-bit timer with modulator
T2I T2O SD
Data direction
BP20/NTE Port 2 BP21 BP22 BP23
MARC4
4-bit CPU core I/O bus
SSI Serial interface
SC
Data direction + alternate function Port 4
Data direction + interrupt control Port 5
BP42 BP40 INT3 T2O SC BP41 BP43 VMI INT3 SD T2I
BP50 INT6
BP52 INT1 BP53 INT1
BP51 INT6
Rev. 4708C-4BMCU-02/04
Pin Configuration
Figure 2. Pinning SSO20 Package
VDD BP40/INT3/SC BP53/INT1 BP52/INT1 BP51/INT6 BP50/INT6 NC OSC1 NC NC
1 2 3 4 5 6 7 8 9 10 20 19 18 17
VSS BP43/INT3/SD BP42/T2O BP41/VMI/T2I BP23 BP22 BP21 BP20/NTE NC NC
ATA6020N
16 15 14 13 12 11
Pin Description
Name Type Function Alternate Function Pin Number SS020 Reset State
VDD VSS NC NC BP20 BP21 BP22 BP23 BP40 BP41 BP42 BP43 BP50 BP51 BP52 BP53 NC NC NC OSC1
- - - - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - - - I
Supply voltage Circuit ground Not connected Not connected Bi-directional I/O line of Port 2.0 Bi-directional I/O line of Port 2.1 Bi-directional I/O line of Port 2.2 Bi-directional I/O line of Port 2.3 Bi-directional I/O line of Port 4.0 Bi-directional I/O line of Port 4.1 Bi-directional I/O line of Port 4.2 Bi-directional I/O line of Port 4.3 Bi-directional I/O line of Port 5.0 Bi-directional I/O line of Port 5.1 Bi-directional I/O line of Port 5.2 Bi-directional I/O line of Port 5.3 Not connected Not connected Not connected Oscillator input
- - - - NTE test mode enable, see also section ''Master Reset'' - - - SC serial clock or INT3 external interrupt input VMI voltage monitor input or T2I external clock input Timer 2 T2O Timer 2 output SD serial data I/O or INT3 external interrupt input INT6 external interrupt input INT6 external interrupt input INT1 external interrupt input INT1 external interrupt input - - - External clock input or external trimming resistor input
1 20 10 11 13 14 15 16 2 17 18 19 6 5 4 3 9 12 7 8
NA NA - - Input Input Input Input Input Input Input Input Input Input Input Input - - - Input
2
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Introduction
The ATA6020N is a member of Atmel's 4-bit single-chip microcontroller family. It contains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction timer/counter, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with integrated RC-oscillators. The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip peripherals. The CPU is based on the HARVARD architecture with physically separated program memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the memory bus and the I/O bus, are used for parallel communication between ROM, RAM and peripherals. This enhances program execution speed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast and efficient processing of hardware events. The MARC4 is designed for the high-level programming language qFORTH. The core includes both, an expression and a return stack. This architecture enables high-level language programming without any loss of efficiency or code density. Figure 3. MARC4 Core
MARC4 Architecture General Description
MARC4 CORE
Reset
Program memory
PC
X Y SP RP
RAM
256 x 4-bit
Reset Clock
Instruction bus Memory bus Instruction decoder TOS CCR ALU
System clock
Sleep
Interrupt controller I/O bus
On-chip peripheral modules
3
4708C-4BMCU-02/04
Components of MARC4 Core
ROM
The core contains ROM, RAM, ALU, a program counter, RAM address registers, an instruction decoder and interrupt controller. The following sections describe each functional block in more detail: The program memory (ROM) is mask programmed with the customer application program during the fabrication of the microcontroller. The ROM is addressed by a 12-bit wide program counter, thus predefining a maximum program bank size of 2 Kbytes. An additional 1-Kbyte of ROM exists, which is reserved for quality control self-test software The lowest user ROM address segment is taken up by a 512-byte Zero page which contains predefined start addresses for interrupt service routines and special subroutines accessible with single byte instructions (SCALL). The corresponding memory map is shown in Figure 4. Look-up tables of constants can also be held in ROM and are accessed via the MARC4's built-in TABLE instruction. Figure 4. ROM Map of ATA6020N
7FFh 1F8h 1F0h 1E8h 1E0h
1E0h 1C0h 180h
I NT 7 I NT 6 I NT 5 I NT 4 I NT 3 I NT 2 I NT 1 I NT 0
SCALL addresses
ROM
(2 K x 8 bit)
Z er o p age
140h 100h 0C0h 080h
1FFh
Zero page
000h
020 h 018h 010h 008h 000 h
040h
008h 000h
$R E SE T $A U T O SL E E P
RAM
The ATA6020N contains 256 x 4-bit wide static random access memory (RAM), which is used for the expression stack. The return stack and data memory are used for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y. Figure 5. RAM Map
(256 x 4-bit) Autosleep FCh FFh Global variables
RAM
Expression stack
3 0 TOS TOS-1 TOS-2 SP
X
RAM address register
Y SP RP
04h 00h 07h 03h TOS-1 Expression stack Return stack Global v variables 11
4-bit
Return stack
0 RP
12-bit
4
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Expression Stack The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arithmetic, I/O and memory reference operations take their operands, and return their results to the expression stack. The MARC4 performs the operations with the top of stack items (TOS and TOS-1). The TOS register contains the top element of the expression stack and works in the same way as an accumulator. This stack is also used for passing parameters between subroutines and as a scratch pad area for temporary storage of data. The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. The return stack can also be used as a temporary storage area. The MARC4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. The two stacks within the RAM have a user definable location and maximum depth. Registers The MARC4 controller has seven programmable registers and one condition code register. They are shown in the following programming model. The program counter is a 12-bit register which contains the address of the next instruction to be fetched from ROM. Instructions currently being executed are decoded in the instruction decoder to determine the internal micro-operations. For linear code (no calls or branches) the program counter is incremented with every instruction cycle. If a branch-, call-, return-instruction or an interrupt is executed, the program counter is loaded with a new address. The program counter is also used with the TABLE instruction to fetch 8-bit wide ROM constants.
Return Stack
Program Counter (PC)
Figure 6. Programming Model
11 0
PC
7 0
Program counter
RP
7
0
0
0
Return stack pointer
SP
7 0
Expression stack pointer
X
7 0
RAM address register (X)
Y
3 0
RAM address register (Y)
TOS
3 0
Top of stack register
CCR
C
--
B
I
Condition code register
Interrupt enable Branch Reserved Carry/borrow
5
4708C-4BMCU-02/04
RAM Address Registers
The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the expression stack. The pointer is automatically pre-incremented if a nibble is moved onto the stack or post-decremented if a nibble is removed from the stack. Every post-decrement operation moves the item (TOS-1) to the TOS register before the SP is decremented. After a reset, the stack pointer has to be initialized with >SP S0 to allocate the start address of the expression stack area. The return stack pointer points to the top element of the 12-bit wide return stack. The pointer automatically pre-increments if an element is moved onto the stack, or it postdecrements if an element is removed from the stack. The return stack pointer increments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initialized via >RP FCh. The X and Y registers are used to address any 4-bit item in RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. By using either the pre-increment or post-decrement addressing mode arrays in RAM can be compared, filled or moved. The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register receives data from the ALU, ROM, RAM or I/O bus. The 4-bit wide condition code register contains the branch, the carry and the interrupt enable flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of the condition code register. The carry/borrow flag indicates that the borrowing or carrying out of the arithmetic logic unit (ALU) occurred during the last arithmetic operation. During shift and rotate operations, this bit is used as a fifth bit. Boolean operations have no effect on the C-flag. The branch flag controls the conditional program branching. Should the branch flag has been set by a previous instruction a conditional branch will cause a jump. This flag is affected by arithmetic, logic, shift, and rotate operations. The interrupt enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. After a reset or on executing the DI instruction, the interrupt enable flag is reset thus disabling all interrupts. The core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing an EI or SLEEP instruction.
Expression Stack Pointer (SP)
Return Stack Pointer (RP)
RAM Address Registers (X and Y)
Top of Stack (TOS)
Condition Code Register (CCR)
Carry/Borrow (C)
Branch (B)
Interrupt Enable (I)
6
ATA6020N
4708C-4BMCU-02/04
ATA6020N
ALU The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU operations affects the carry/borrow and branch flag in the condition code register (CCR). Figure 7. ALU Zero-address Operations
RAM
SP
TOS-1 TOS-2 TOS-3 TOS-4 CCR ALU
TOS
I/O Bus
The I/O ports and the registers of the peripheral modules are I/O mapped. All communication between the core and the on-chip peripherals take place via the I/O bus and the associated I/O control. With the MARC4 IN and OUT instructions, the I/O bus allows a direct read or write access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip peripherals is described in the section "Peripheral Modules". The I/O bus is internal and is not accessible by the customer on the final microcontroller device, but it is used as the interface for the MARC4 emulation (see section "Emulation"). The MARC4 instruction set is optimized for the high level programming language qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to generate a fast and compact program code. The CPU has an instruction pipeline allowing the controller to prefetch an instruction from ROM at the same time as the present instruction is being executed. The MARC4 is a zero address machine, the instructions containing only the operation to be performed and no source or destination address fields. The operations are implicitly performed on the data placed on the stack. There are one- and two-byte instructions which are executed within 1 to 4 machine cycles. A MARC4 machine cycle is made up of two system clock cycles (SYSCL). Most of the instructions are only one byte long and are executed in a single machine cycle. For more information refer to the "MARC4 Programmer's Guide". The MARC4 can handle interrupts with eight different priority levels. They can be generated from the internal and external interrupt sources or by a software interrupt from the CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the service routine in ROM (see Table 1 on page 9). The programmer can postpone the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still be registered, but the interrupt routine only starts after the I-flag is set. All interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module (see section "Peripheral Modules").
Instruction Set
Interrupt Structure
7
4708C-4BMCU-02/04
Figure 8. Interrupt Handling
INT7
7 6 Priority Level 5 4 3 2 1 0
Main / Autosleep INT3 INT5
INT7 active RTI
INT5 active RTI
INT2 INT3 active RTI INT2 pending INT2 active RTI SWI0
INT0 pending
INT0 active RTI Main / Autosleep
Time
Interrupt Processing
In order to process the eight interrupt levels, the MARC4 includes an interrupt controller with two 8-bit wide interrupt pending and interrupt active registers. The interrupt controller samples all interrupt requests during every non-I/O instruction cycle and latches these in the interrupt pending register. If no higher priority interrupt is present in the interrupt active register, it signals the CPU to interrupt the current program execution. If the interrupt enable bit is set, the processor enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to the service routine is executed and the current PC is saved on the return stack. An interrupt service routine is completed with the RTI instruction. This instruction resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. When the interrupt enable flag is reset (triggering of interrupt routines are disabled), the execution of new interrupt service routines is inhibited but not the logging of the interrupt requests in the interrupt pending register. The execution of the interrupt is delayed until the interrupt enable flag is set again. Note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). It should be noted that automatic stacking of the RBR is not carried out by the hardware and so if ROM banking is used, the RBR must be stacked on the expression stack by the application program and restored before the RTI. After a master reset (power-on, brown-out or watchdog reset), the interrupt enable flag and the interrupt pending and interrupt active register are all reset.
Interrupt Latency
The interrupt latency is the time from the occurrence of the interrupt to the interrupt service routine being activated. This is extremely short (taking between 3 to 5 machine cycles depending on the state of the core).
8
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Table 1. Interrupt Priority Table
Interrupt INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Priority lowest | | | | |
ROM Address 040h 080h 0C0h 100h 140h 180h 1C0h 1E0h
Interrupt Opcode C8h (SCALL 040h) D0h (SCALL 080h) D8h (SCALL 0C0h) E8h (SCALL 100h) E8h (SCALL 140h) F0h (SCALL 180h) F8h (SCALL 1C0h) FCh (SCALL 1E0h)
Function Software interrupt (SWI0) External hardware interrupt, any edge at BP52 or BP53 Timer 1 interrupt SSI interrupt or external hardware interrupt at BP40 or BP43 Timer 2 interrupt Software interrupt (SW15) External hardware interrupt, at any edge at BP50 or BP51 Voltage monitor (VM) interrupt
highest
Table 2. Hardware Interrupts
Interrupt Mask Interrupt INT1 INT2 INT3 INT4 INT6 INT7
Register Bit
Interrupt Source Any edge at BP52 Any edge at BP53 Timer 1 SSI buffer full/empty or BP40/BP43 interrupt Timer 2 compare match/overflow Any edge at BP50 Any edge at BP51 External/internal voltage monitoring
P5CR T1M SISC T2CM P5CR VCM
P52M1, P52M2 P53M1, P53M2 T1IM SIM T2IM P50M1, P50M2 P51M1, P51M2 VIM
Software Interrupts
The programmer can generate interrupts by using the software interrupt instruction (SWI), which is supported in qFORTH by predefined macros named SWI0...SWI7. The software triggered interrupt operates exactly like any hardware triggered interrupt. The SWI instruction takes the top two elements from the expression stack and writes the corresponding bits via the I/O bus to the interrupt pending register. Therefore, by using the SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled for later execution. In the ATA6020N, there are eleven hardware interrupt sources with seven different levels. Each source can be masked individually by mask bits in the corresponding control registers. An overview of the possible hardware configurations is shown in Table 2.
Hardware Interrupts
9
4708C-4BMCU-02/04
Master Reset
The master reset forces the CPU into a well-defined condition. It is unmaskable and is activated independent of the current program state. It can be triggered by either initial supply power-up, a short collapse of the power supply, the brown-out detection circuitry, a watchdog time-out, or an external input clock supervisor stage (see Figure 9). A master reset activation will reset the interrupt enable flag, the interrupt pending register and the interrupt active register. During the power-on reset phase, the I/O bus control signals are set to reset mode, thereby, initializing all on-chip peripherals. All bi-directional ports are set to input mode. Attention: During any reset phase, the BP20/NTE input is driven towards VDD by an additional internal strong pull-up transistor. This pin must not be pulled down to VSS during reset by any external circuitry representing a resistor of less than 150 kW. Releasing the reset results in a short call instruction (opcode C1h) to the ROM address 008h. This activates the initialization routine $RESET which in turn has to initialize all necessary RAM variables, stack pointers and peripheral configuration registers.
Figure 9. Reset Configuration
VV DD DD Pull-up CL CL NRST res res Reset Reset timer timer Internal Internal reset reset
CL=SYSCL/4 CL=SYSCL/4 Power-on Power-on reset reset VDD VDD VSS V SS VDD DD VSS SS CWD CWD
Brown-out Brown-out detection detection
WatchWatchdog res dog res
Ext. clock Ext. clock supervisor supervisor
ExIn ExIn
Power-on Reset and Brown-out Detection
The ATA6020N has a fully integrated power-on reset and brown-out detection circuitry. For reset generation no external components are needed. These circuits ensure that the core is held in the reset state until the minimum operating supply voltage has been reached. A reset condition will also be generated should the supply voltage drop momentarily below the minimum operating level except when a power-down mode is activated (the core is in SLEEP mode and the peripheral clock is stopped). In this power-down mode the brown-out detection is disabled. Two values for the brown-out voltage threshold are programmable via the BOT bit in the SC-register.
10
ATA6020N
4708C-4BMCU-02/04
ATA6020N
A power-on reset pulse is generated by a VDD rise across the default BOT voltage level (3.0 V). A brown-out reset pulse is generated when VDD falls below the brown-out voltage threshold. Two values for the brown-out voltage threshold are programmable via the BOT-bit in the SC-register. When the controller runs in the upper supply voltage range with a high system clock frequency, the high threshold must be used. When it runs with a lower system clock frequency, the low threshold and a wider supply voltage range may be chosen. For further details, see the electrical specification and the SCregister description for BOT programming. Figure 10. Brown-out Detection
VDD
4.0 V 3.0 V
td CPU Reset BOT = 1 td CPU Reset BOT = 0 td = 1.5 ms (typically) td
t
BOT = 1, low brown-out voltage threshold. (3.0 V is the reset value). BOT = 0, high brown-out voltage threshold (4.0 V). Watchdog Reset The watchdog's function can be enabled at the WDC-register and triggers a reset with every watchdog counter overflow. To suppress the watchdog reset, the watchdog counter must be regularly reset by reading the watchdog register address (CWD). The CPU reacts in exactly the same manner as a reset stimulus from any of the above sources. The external input clock supervisor function can be enabled if the external input clock is selected within the CM- and SC-registers of the clock module. The CPU reacts in exactly the same manner as a reset stimulus from any of the above sources. The voltage monitor consists of a comparator with internal voltage reference. It is used to supervise the supply voltage or an external voltage at the VMI pin. The comparator for the supply voltage has two internal programmable thresholds: one lower threshold (4.0 V) and one higher threshold (5.0 V). For external voltages at the VMI pin, the comparator threshold is set to VBG = 1.25 V. The VMS-bit indicates if the supervised voltage is below (VMS = 0) or above (VMS = 1) this threshold. An interrupt can be generated when the VMS-bit is set or reset to detect a rising or falling slope. A voltage monitor interrupt (INT7) is enabled when the interrupt mask bit (VIM) is reset in the VMC-register.
External Clock Supervisor
Voltage Monitor
11
4708C-4BMCU-02/04
Figure 11. Voltage Monitor
VDD Voltage monitor BP41/ VMI IN OUT INT7
VMC
VM2
VM1 VM0
VIM
VMST
-
-
res VMS
Voltage Monitor Control/Status Register
Bit 3 VMC: Write VMST: Read VM2 -- Bit 2 VM1 -- Bit 1 VM0 reserved Bit 0 VIM VMS
Primary register address: 'F'hex Reset value: 1111b Reset value: xx11b
VM2: Voltage monitor Mode bit 2 VM1: Voltage monitor Mode bit 1 VM0: Voltage monitor Mode bit 0 Table 3. Voltage Monitor Modes
VM2 1 1 1 1 0 0 0 0 VM1 1 1 0 0 1 1 0 0 VM0 1 0 1 0 1 0 1 0 Function Disable voltage monitor External (VIM input), internal reference threshold (1.25 V), interrupt with negative slope Not allowed External (VMI input), internal reference threshold (1.25 V), interrupt with positive slope Internal (supply voltage), high threshold (5.0 V), interrupt with negative slope Not allowed Internal (supply voltage), low threshold (4.0 V), interrupt with negative slope Not allowed
VIM Voltage Interrupt Mask bit * * * * VIM = 0, voltage monitor interrupt is enabled VIM = 1, voltage monitor interrupt is disabled VMS = 0, the voltage at the comparator input is below VRef VMS = 1, the voltage at the comparator input is above VRef
VMS Voltage Monitor Status bit
12
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Figure 12. Internal Supply Voltage Supervisor
Low threshold VMS = 1 VDD High threshold
5.0 V 4.0 V
Low threshold VMS = 0 High threshold
Figure 13. External Input Voltage Supervisor
Internal reference level VMI Negative slope VMS = 1 1.25 V VMS = 0 Positive slope Interrupt negative slope t VMS = 0 Interrupt positive slope VMS = 1
Clock Generation
Clock Module The ATA6020N contains a clock module with two different internal RC-oscillator types. OSC1 can be used as input for external clocks or to connect an external trimming resistor for RC-oscillator 2. All necessary circuitry, except the trimming resistor, is integrated on-chip. One of these oscillator types or an external input clock can be selected to generate the system clock (SYSCL). In applications that do not require exact timing, it is possible to use the fully integrated RC-oscillator 1 without any external components. The RC-oscillator 1 center frequency tolerance is better than 50%. RC-oscillator 2 is a trimmable oscillator whereby the oscillator frequency can be trimmed with an external resistor attached between OSC1 and GND. In this configuration, RC-oscillator 2 frequency can be maintained stable to within a tolerance of 15% over the full operating temperature and voltage range. The clock module is programmable via software with the clock management register (CM) and the system configuration register (SC). The required oscillator configuration can be selected with the OS1-bit and the OS0-bit in the SC-register. A programmable 4-bit divider stage allows the adjustment of the system clock speed. A special feature of the clock management is that an external oscillator may be used and switched on and off via a port pin for the power-down mode. Before the external clock is switched off, the internal RC-oscillator 1 must be selected with the CCS-bit and then the SLEEP mode may be activated. In this state an interrupt can wake up the controller with the RC-oscillator, and the external oscillator can be activated and selected by software. A synchronization stage avoids clock periods that are too short if the clock source or the clock speed is changed. If an external input clock is selected, a supervisor circuit monitors the external input and generates a hardware reset if the external clock source fails or drops below 500 kHz for more than 1 ms.
13
4708C-4BMCU-02/04
Figure 14. Clock Module
OSC1 Oscin
RC oscillator 1 Ext. clock
ExIn ExOut Stop Stop RCOut1 Control IN1 Cin IN2 Divider /2 /2 /2 /2
SYSCL
RC oscillator2
RTrim RCOut2 Stop Sleep WDL NSTOP CCS CSS1 CSS0 Cin/16
Osc-Stop CM
SUBCL
SC
BOT
---
OS1
OS0
Table 4. Clock Modes
Clock Source for SYSCL Mode 1 2 OS1 1 0 OS0 1 1 CCS = 1 RC-oscillator 1 (internal) RC-oscillator 1 (internal) CCS = 0 External input clock RC-oscillator 2 with external trimming resistor Clock Source for SUBCL Cin/16 Cin/16
The clock module generates two output clocks. One is the system clock (SYSCL) and the other the periphery (SUBCL). The SYSCL can supply the core and the peripherals and the SUBCL can supply only the peripherals with clocks. The modes for clock sources are programmable with the OS1-bit and OS0-bit in the SC-register and the CCS-bit in the CM-register. Oscillator Circuits and External Clock Input Stage RC-oscillator 1 Fully Integrated The ATA6020N consists of two different internal RC-oscillators and one external clock input stage. For timing insensitive applications, it is possible to use the fully integrated RC-oscillator 1. It operates without any external components and saves additional costs. The RC-oscillator 1 center frequency tolerance is better than 50% over the full temperature and voltage range. The basic center frequency of the RC-oscillator 1 is fO 4.0 MHz The RC-oscillator 1 is selected by default after power-on reset.
14
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Figure 15. RC-oscillator 1
RC-oscillator 1 RcOut1 Stop RcOut1 Osc-Stop
Control
External Input Clock
The OSC1 can be driven by an external clock source provided it meets the specified duty cycle, rise and fall times and input levels. Additionally, the external clock stage contains a supervisory circuit for the input clock. The supervisor function is controlled via the OS1, OS0-bit in the SC-register and the CCS-bit in the CM-register. If the external input clock fails and CCS = 0 is set in the CM-register, the supervisory circuit generates a hardware reset. The input clock has failed if the frequency is less than 500 kHz for more than 1 ms. Figure 16. External Input Clock
Ext. input clock Ext. Clock OSC1 ExIn Stop ExOut
RcOut1 Osc-Stop CCS
Clock monitor
Res
Table 5. Supervisor Function Control Bits
OS1 1 1 x OS0 1 1 0 CCS 0 1 x Supervisor Reset Output (Res) Enable Disable Disable
RC-oscillator 2 with External Trimming Resistor
The RC-oscillator 2 is a high resolution trimmable oscillator whereby the oscillator frequency can be trimmed with an external resistor between OSC1 and V DD. In this configuration, the RC-oscillator 2 frequency can be maintained stable to within a tolerance of 10% over the full operating temperature and voltage range from VDD = 3.5 V to 5.5 V. For example: An output frequency at the RC-oscillator 2 of 1.6 MHz, can be obtained by connecting a resistor Rext = 47 kW (see Figure 17 on page 16).
15
4708C-4BMCU-02/04
Figure 17. RC-oscillator 2
RC-oscillator 2 OSC1 RTrim Rext Stop RcOut2 RcOut2 Osc-Stop
Clock Management
The clock management register controls the system clock divider and synchronization stage. Writing to this register triggers the synchronization cycle.
Clock Management Register (CM)
Bit 3 CM NSTOP Bit 2 CCS Bit 1 CSS1 Bit 0 CSS0
Auxiliary register address: '3'hex Reset value: 1111b
NSTOP
Not STOP peripheral clock NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode Core Clock Select CCS = 1, the internal RC-oscillator 1 generates SYSCL CCS = 0, an external clock source or the RC-oscillator 2 with the external resistor at OSC1 generates SYSCL dependent on the setting of OS0 and OS1 in the system configuration register Core Speed Select 1 Core Speed Select 0
CCS
CSS1 CSS0
Table 6. Core Speed Select
CSS1 0 1 1 0 CSS0 0 1 0 1 Divider 16 8 4 2 Note - Reset value - -
16
ATA6020N
4708C-4BMCU-02/04
ATA6020N
System Configuration Register (SC)
Bit 3 SC: write BOT Bit 2 - Bit 1 OS1 Bit 0 OS0 Reset value: 1x11b Primary register address: '3'hex
BOT
Brown-Out Threshold BOT = 1, low brown-out voltage threshold (3.0 V) BOT = 0, high brown-out voltage threshold (4.0 V) Oscillator Select 1 Oscillator Select 0
OS1 OS0
Table 7. Oscillator Select
Mode 1 2 Note: OS1 1 0 OS0 1 1 Input for SUBCL Cin/16 Cin/16 Selected Oscillators RC-oscillator 1 and external input clock RC-oscillator 1 and RC-oscillator 2
If bit CCS = 0 in the CM-register, the RC-oscillator 1 always stops.
Power-down Modes
The sleep mode is a shut-down condition which is used to reduce the average system power consumption in applications where the microcontroller is not fully utilized. In this mode, the system clock is stopped. The sleep mode is entered via the SLEEP instruction. This instruction sets the interrupt enable bit (I) in the condition code register to enable all interrupts and stops the core. During the sleep mode the peripheral modules remain active and are able to generate interrupts. The microcontroller exits the sleep mode by carrying out any interrupt or a reset. The sleep mode can only be kept when none of the interrupt pending or active register bits are set. The application of the $AUTOSLEEP routine ensures the correct function of the sleep mode. The total power consumption is directly proportional to the active time of the microcontroller. For a rough estimation of the expected average system current consumption, the following formula should be used: Itotal (VDD,fsyscl) = ISleep + (IDD tactive/ttotal) IDD depends on VDD and fsyscl The ATA6020N has various power-down modes. During the sleep mode the clock for the MARC4 core is stopped. With the NSTOP-bit in the clock management register (CM), it is programmable if the clock for the on-chip peripherals is active or stopped during the sleep mode. If the clock for the core and the peripherals is stopped the selected oscillator is switched off. Table 8. Power-down Modes
Mode Active Power-down SLEEP Note: CPU Core RUN SLEEP SLEEP Osc-Stop(1) NO NO YES Brown-out Function Active Active STOP RC-oscillator 1 RC-oscillator 2 RUN RUN STOP External Input Clock YES YES STOP
1. Osc-Stop = SLEEP and NSTOP and WDL
17
4708C-4BMCU-02/04
Peripheral Modules
Addressing Peripherals
Accessing the peripheral modules takes place via the I/O bus (see Figure 18). The IN or OUT instructions allow direct addressing of up to 16 I/O modules. A dual register addressing scheme has been adopted to enable direct addressing of the primary register. To address the auxiliary register, the access must be switched with an auxiliary switching module. Thus, a single IN (or OUT) to the module address will read (or write into) the modules primary register. Accessing the auxiliary register is performed with the same instruction preceded by writing the module address into the auxiliary switching module. Byte wide registers are accessed by multiple IN (or OUT) instructions. For more complex peripheral modules, with a larger number of registers, extended addressing is used. In this case, a bank of up to 16 subport registers are indirectly addressed with the subport address. The first OUT-instruction writes the subport address to the sub-address register, the second IN or OUT instruction reads data from or writes data to the addressed subport.
Figure 18. Example of I/O Addressing
Module ASW Module M1
(Address Pointer) Subaddress Reg. Auxiliary Switch Module 1 Bank of Primary Regs. Subport FH Subport EH
Module M2
Aux. Reg.
Module M3
5
Primary Reg.
Subport 1 Subport 0 2 4 Primary Reg. 3
Primary Reg.
6
I/O bus
to other modules
Indirect Subport Access
Dual Register Access (Primary Register Write)
3
Single Register Access (Primary Register Write)
6
(Subport Register Write)
1 2
Addr. (SPort) Addr. (M1) OUT SPort_Data Addr. (M1) OUT
Prim._Data Addr. (M2) OUT (Auxiliary Register Write)
Prim._Data Addr. (M3) OUT (Primary Register Read)
(Subport Register Read) 1 Addr. (SPort) Addr. (M1) OUT Addr. (M1) IN (Subport Register Write Byte) 1
2 2
4 5
Addr. (M2) Addr. (ASW) OUT Aux._Data Addr. (M2) OUT (Primary Register Read)
6
Addr. (M3) IN
Example of qFORTH Program Code
2
3
Addr. (M2) IN (Auxiliary Register Read )
Addr. (SPort) Addr. (M1) OUT SPort_Data (lo) Addr. (M1) SPort_Data (hi) Addr. (M1) (Subport Register Read Byte) OUT OUT
4
5
Addr. (M2) Addr. (ASW) OUT Addr. (M2) IN (Auxiliary Register Write Byte)
1 2 2
Addr. (SPort) Addr. (M1) OUT Addr. (M1) IN (hi) Addr. (M1) IN (lo)
4 5 5
Addr. (M2) Addr. (ASW) OUT Aux._Data (lo) Addr. (M2) Aux._Data (hi) Addr. (M2) OUT OUT
Addr. (ASW) = Auxililiary Switch Module Address Addr. (Mx) = Module Mx Address Addr. (SPort) = Subport Address Prim._Data = Data to be written into Primary Register Aux._Data = Data to be written into Auxiliary Register Aux._Data (lo) = Data to be written into Auxiliary Register (low nibble)
Aux._Data (hi) = Data to be written into Auxiliary Register (high nibble) SPort_Data (lo) = Data to be written into Subport (low nibble) SPort_Data (hi) = Data to be written into Subport (high nibble) (lo) = SPort_Data (low nibble) (hi) = SPort_Data (high nibble)
18
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Table 9. Peripheral Addresses
Port Address 2 Aux. 3 Aux. 4 Aux. 5 Aux. 6 7 0 1 2 3 4 5 6 7 8 9 A B-F 8 9 Aux. A Aux. B C D E F ASW STB SRB SIC1 SISC SIC2 -- -- RBR -- VMC VMST W R W 0000b -- 1111b xx11b W W R W W/R W 1111b xxxx xxxxb xxxx xxxxb 1111b 1x11b 1111b Name P2DAT P2CR SC CWD CM P4DAT P4CR P5DAT P5CR -- T12SUB Support address T2C T2M1 T2M2 T2CM T2CO1 T2CO2 -- -- T1C1 T1C2 WDC W W W W W W -- -- W W W 0000b 1111b 1111b 0000b 1111b 1111 1111b -- -- 1111b x111b 1111b Timer 2 control register Timer 2 mode register 1 Timer 2 mode register 2 Timer 2 compare mode register Timer 2 compare register 1 Timer 2 compare register 2 (byte) Reserved Reserved Timer 1 control register 1 Timer 1 control register 2 Watchdog control register Reserved Auxiliary/switch register Serial transmit buffer (byte) Serial receive buffer (byte) Serial interface control register 1 Serial interface status/control register Serial interface control register 2 Reserved Reserved ROM bank switch register Reserved Voltage monitor control register Voltage monitor status register M3 M3 12 12 M3 6 M2 ASW M2 18 48 48 46 48 47 M1 M1 M1 27 27 28 M1 M1 M1 M1 M1 M1 35 35 37 38 38 38 W -- Write/Read W/R W W R W W/R W W/R W Reset Value 1111b 1111b 1x11b xxxxb 1111b 1111b 1111 1111b 1111b 1111 1111b Register Function Port 2 - data register/pin data Port 2 - control register Port 3 - system configuration register Watchdog reset Port 3 - clock management register Port 4 - data register/pin data Port 4 - control register (byte) Port 5 - data register/pin data Port 5 - control register (byte) Reserved Data to Timer 1/2 subport M1 18 M2 M3 M3 M2 M2 Module Type M2 See Page 21 21 17 11 16 24 24 23 23
19
4708C-4BMCU-02/04
Bi-directional Ports
Ports 2, 4 and 5 are 4 bits wide. All ports may be used for data input or output. All ports are equipped with Schmitt trigger inputs and a variety of mask options for open-drain, open-source, full-complementary outputs, pull-up and pull-down transistors. All Port Data Registers (PxDAT) are I/O mapped to the primary address register of the respective port address and the Port Control Register (PxCR), to the corresponding auxiliary register. There are three different directional ports available: Port 2 Port 5 Port 4 4-bit wide bitwise-programmable I/O port. 4-bit wide bitwise-programmable bi-directional port with optional static pull-ups and programmable interrupt logic. 4-bit wide bitwise-programmable bi-directional port also provides the I/O interface to Timer 2, SSI, voltage monitor input and external interrupt input.
Bi-directional Port 2
This, and all other bi-directional ports include a bitwise-programmable Control Register (P2CR), which enables the individual programming of each port bit as input or output. It also opens up the possibility of reading the pin condition when in output mode. This is a useful feature for self-testing and for serial bus applications. Port 2, however, has an increased drive capability and an additional low resistance pullup/-down transistor mask option. Care should be taken connecting external components to BP20/NTE. During any reset phase, the BP20/NTE input is driven towards VDD by an additional internal strong pull-up transistor. This pin must not be pulled down (active or passive) to VSS during reset by any external circuitry representing a resistor of less than 150 kW. This prevents the circuit from unintended switching to test mode enable through the application circuitry at pin BP20/NTE. Resistors less than 150 kW might lead to an undefined state of the internal test logic thus disabling the application firmware. To avoid any conflict with the optional internal pull-down transistors, BP20 handles the pull-down options in a different way than all other ports. BP20 is the only port that switches off the pull-down transistors during reset.
Figure 19. Bi-directional Port 2
I/O Bus Pull-up
(1) (1)
VDD Static Pull-up
(Data out) I/O Bus D S Master reset I/O Bus Q P2DATy
(1)
BP2y
(1)
VDD
D SQ P2CRy
(1)
(1)
Static Pull-down
Pull-down (Direction)
(1) Mask
options
20
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Port 2 Data Register (P2DAT)
Primary register address: '2'hex Bit 3 P2DAT P2DAT3 Bit 2 P2DAT2 Bit 1 P2DAT1 Bit 0 P2DAT0 Reset value: 1111b
Bit 3 = MSB, Bit 0 = LSB Port 2 Control Register (P2CR)
Auxiliary register address: '2'hex Bit 3 P2CR P2CR3 Bit 2 P2CR2 Bit 1 P2CR1 Bit 0 P2CR0 Reset value: 1111b
Value: 1111b means all pins in input mode Table 10. Port 2 Control Register
Code 3210 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx Function BP20 in input mode BP20 in output mode BP21 in input mode BP21 in output mode BP22 in input mode BP22 in output mode BP23 in input mode BP23 in output mode
Bi-directional Port 5
This, and all other bi-directional ports include a bitwise-programmable Control Register (P5CR), which allows individual programming of each port bit as input or output. It also opens up the possibility of reading the pin condition when in output mode. This is a useful feature for self testing and for serial bus applications. The port pins can also be used as external interrupt inputs (see Figure 20 on page 22 and Figure 21 on page 22). The interrupts (INT1 and INT6) can be masked or independently configured to trigger on either edge. The interrupt configuration and port direction is controlled by the Port 5 Control Register (P5CR). An additional low resistance pullup/-down transistor mask option provides an internal bus pull-up for serial bus applications. The Port 5 Data Register (P5DAT) is I/O mapped to the primary address register of address '5'h and the Port 5 Control Register (P5CR) to the corresponding auxiliary register. The P5CR is a byte-wide register and is configured by writing first the low nibble then the high nibble (see section "Addressing Peripherals").
21
4708C-4BMCU-02/04
Figure 20. Bi-directional Port 5
I/O Bus VDD Pull-up
(1) (1)
VDD
Static pull-up
VDD (Data out) I/O Bus D Q P5DATy S Master reset IN enable
(1) (1) (1) (1)
BP5y
VDD
Static pull-down
(1)
Mask options
Pull-down
Figure 21. Port 5 External Interrupts
INT1
Data in
BP52
INT6
Data in Bi-directional Port IN_Enable
BP51
Bi-directional Port IN_Enable
I/O-bus
I/O-bus
Data in
BP53
Data in Bi-directional Port IN_Enable
Decoder Decoder Decoder Decoder BP50
Bi-directional Port IN_Enable
P5CR
P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1
22
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Port 5 Data Register (P5DAT)
Primary register address:'5'hex Bit 3 P5DAT P5DAT3 Bit 2 P5DAT2 Bit 1 P5DAT1 Bit 0 P5DAT0 Reset value: 1111b
Port 5 Control Register (P5CR) Byte Write
Auxiliary register address:'5'hex Bit 3 P5CR First write cycle Second write cycle P51M2 Bit 7 P53M2 Bit 2 P51M1 Bit 6 P53M1 Bit 1 P50M2 Bit 5 P52M2 Bit 0 P50M1 Bit 4 P52M1 Reset value: 1111b Reset value: 1111b
P5xM2, P5xM1 - Port 5x Interrupt Mode/Direction Code Table 11. Port 5 Control Register
Auxiliary Address:'5'hex Code 3210 xx11 xx01 xx10 xx00 11xx 01xx 10xx 00xx Function BP50 in input mode - interrupt disabled BP50 in input mode - rising edge interrupt BP50 in input mode - falling edge interrupt BP50 in output mode - interrupt disabled BP51 in input mode - interrupt disabled BP51 in input mode - rising edge interrupt BP51 in input mode - falling edge interrupt BP51 in output mode - interrupt disabled First Write Cycle Second Write Cycle Code 3210 xx11 xx01 xx10 xx00 11xx 01xx 10xx 00xx Function BP52 in input mode - interrupt disabled BP52 in input mode - rising edge interrupt BP52 in input mode - falling edge interrupt BP52 in output mode - interrupt disabled BP53 in input mode - interrupt disabled BP53 in input mode - rising edge interrupt BP53 in input mode - falling edge interrupt BP53 in output mode - interrupt disabled
Bi-directional Port 4
The bi-directional Port 4 is both a bitwise configurable I/O port and provides the external pins for the Timer 2, SSI and the voltage monitor input (VMI). As a normal port, it performs in exactly the same way as bi-directional Port 2 (see Figure 19 on page 20). Two additional multiplexes allow data and port direction control to be passed over to other internal modules (Timer 2, VM or SSI). The I/O-pins for the SC and SD lines have an additional mode to generate an SSI-interrupt. All four Port 4 pins can be individually switched by the P4CR-register. Figure 22 on page 24 shows the internal interfaces to bi-directional Port 4.
23
4708C-4BMCU-02/04
Figure 22. Bi-directional Port 4
I/O Bus Intx PxMRy VDD
(1) (1) (1)
VDD
Static pull-up
PIn POut I/O Bus D Q PxDATy S Master reset I/O Bus D
Pull-up
BPxy
(1)
VDD
(Direction) S Q Pull-down
(1)
(1)
Static pull-down
PxCRy PDir
(1) Mask
options
Port 4 Data Register (P4DAT)
Primary register address: '4'hex Bit 3 P4DAT P4DAT3 Bit 2 P4DAT2 Bit 1 P4DAT1 Bit 0 P4DAT0 Reset value: 1111b
Port 4 Control Register (P4CR) Byte Write
Auxiliary register address: '4'hex Bit 3 P4CR First write cycle Second write cycle P41M2 Bit 7 P43M2 Bit 2 P41M1 Bit 6 P43M1 Bit 1 P40M2 Bit 5 P42M2 Bit 0 P40M1 Bit 4 P42M1 Reset value: 1111b Reset value: 1111b
P4xM2, P4xM1 - Port 4x Interrupt Mode/Direction Code Table 12. Port 4 Control Register
Auxiliary Address: '4'hex Code 3210 xx11 xx10 xx01 xx00 11xx 10xx 01xx 00xx Function BP40 in input mode BP40 in output mode BP40 enable alternate function (SC for SSI) BP40 enable alternate function (falling edge interrupt input for INT3) BP41 in input mode BP41 in output mode BP41 enable alternate function (VMI for voltage monitor input) BP41 enable alternate function (T2I external clock input for Timer 2) First Write Cycle Second Write Cycle Code 3210 xx11 xx10 xx0x 11xx 10xx 01xx 00xx - Function BP42 in input mode BP42 in output mode BP42 enable alternate function (T2O for Timer 2) BP43 in input mode BP43 in output mode BP43 enable alternate function (SD for SSI) BP43 enable alternate function (falling edge interrupt input for INT3) -
24
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Universal Timer/Counter/ Communication Module (UTCM) The Universal Timer/counter/Communication Module (UTCM) consists of Timer 1, Timer 2 and a Synchronous Serial Interface (SSI). * * * Timer 1 is an interval timer that can be used to generate periodical interrupts and as prescaler for Timer 2, the serial interface and the watchdog function. Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O). The SSI operates as a two-wire serial interface or as a shift register for modulation. The modulator units work together with the timers and shift the data bits out of the shift register.
There is a multitude of modes in which the timers and the serial interface can work together. Figure 23. UTCM Block Diagram
SYSCL SUBCL MUX Interval/Prescaler T1OUT MUX Compare 2/1 POUT MUX DCG Compare 2/2 Control 8-bit Counter 2/2 INT4 from clock module
Timer 1
Watchdog NRST INT2
Timer 2
4-bit Counter 2/1 Modulator 2 I/O bus T2O
T2I
TOG2
SSI
Receive-buffer 8-bit Shift-register Transmit-buffer
SCL
MUX
Control INT3
SC SD
Timer 1
Timer 1 is an interval timer which can be used to generate periodic interrupts and as a prescaler for Timer 2, Timer 3, the serial interface and the watchdog function. Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL or SYSCL. The timer output signal can be used as a prescaler clock or as SUBCL and as source for the Timer 1 interrupt. Because of other system requirements Timer 1 output T1OUT is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes) the output T1OUT is stopped (T1OUT = 0). Nevertheless, Timer 1 can be active in SLEEP and generate Timer 1 interrupts. The interrupt is maskable via the T1IM bit and the SUBCL can be bypassed via the T1BP bit of the T1C2 register. The time interval for the timer output can be programmed via the Timer 1 control register T1C1. This timer starts running automatically after any power-on reset! If the watchdog function is not activated, the timer can be restarted by writing into the T1C1 register with T1RM = 1.
25
4708C-4BMCU-02/04
Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The watchdog timer is a 3-bit counter that is supplied by a separate output of Timer 1. It generates a system reset when the 3-bit counter overflows. To avoid this, the 3-bit counter must be reset before it overflows. The application software has to accomplish this by reading the CWD register. After power-on reset the watchdog must be activated by software in the $RESET initialization routine. There are two watchdog modes, in one mode the watchdog can be switched on and off by software, in the other mode the watchdog is active and locked. This mode can only be stopped by carrying out a system reset. The watchdog timer operation mode and the time interval for the watchdog reset can be programmed via the watchdog control register (WDC). Figure 24. Timer 1 Module
SYSCL SUBCL WDCL CL1
MUX
14-bit Prescaler
4-bit Watchdog
NRST
INT2 T1CS T1MUX T1BP T1IM T1OUT
Figure 25. Timer 1 and Watchdog
T1C1 T1RM T1C2 T1C1 T1C0 3 Write of the T1C1 register T1MUX T1IM=0 INT2 T1IM=1 T1OUT RES Q1 Q2 Q3 Q4 Q5 CL1 CL Q6 Q8 Q8 Q11 Q11 Q14 SUBCL Q14 Watchdog Divider/8 T1C2 T1BP T1IM
Decoder
MUX for interval timer
Decoder
2
MUX for watchdog timer WDCL
RES Read of the CWD register Divider RESET RESET (NRST)
WDC WDL
WDR WDT1 WDT0
Watchdog mode control
26
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Timer 1 Control Register 1 (T1C1)
Bit 3 T1C1 T1RM Bit 2 T1C2 Bit 1 T1C1 Bit 0 T1C0 Reset value: 1111b Address: '7'hex - Subaddress: '8'hex
Bit 3 = MSB, Bit 0 = LSB
T1RM T1RM = 0, write access without Timer 1 restart T1RM = 1, write access with Timer 1 restart Note: If WDL = 0, Timer 1 restart is impossible Timer 1 Control bit 2 Timer 1 Control bit 1 Timer 1 Control bit 0 Timer 1 Restart Mode
T1C2 T1C1 T1C0
The three bits T1C[2:0] select the divider for Timer 1. The resulting time interval depends on this divider and the timer 1 input clock source. The timer input can be supplied by the system clock or via clock management. If the clock management generates the SUBCL, the selected input clock from the RC oscillator or an external clock is divided by 16 . Table 13. Timer 1 Control Bits
T1C2 0 0 0 0 1 1 1 1 Note: T1C1 0 0 1 1 0 0 1 1 T1C0 0 1 0 1 0 1 0 1 Divider 2 4 8 16 32 256 2048 16384 Time Interval with SUBCL from Clock Management Tin 32 Tin 64 Tin 128 Tin 256 Tin 512 Tin 4096 Tin 32768 Tin 262144 Time Interval with SYSCL = 2/1 MHz 1 s/2 s 2 s/4 s 4 s/8 s 8 s/16 s 16 s/32 s 128 s/256 s 1024 s/2048 s 8192 s/16384 s
Tin: input clock period = 1/Cin (see Figure 14 on page 14)
Timer 1 Control Register 2 (T1C2)
Bit 3 T1C2 - Bit 2 T1BP Bit 1 T1CS Bit 0 T1IM
Address: '7'hex - Subaddress: '9'hex Reset value: x111b
Bit 3 = MSB, Bit 0 = LSB
T1BP Timer 1 SUBCL ByPassed T1BP = 1, TIOUT = T1MUX T1BP = 0, T1OUT = SUBCL Timer 1 input Clock Select T1CS = 1, CL1 = SUBCL (see Figure 28 on page 30) T1CS = 0, CL1 = SYSCL (see Figure 28 on page 30) Timer 1 Interrupt Mask T1IM = 1, disables Timer 1 interrupt T1IM = 0, enables Timer 1 interrupt
T1CS
T1IM
27
4708C-4BMCU-02/04
Watchdog Control Register (WDC)
Bit 3 WDC WDL Bit 2 WDR Bit 1 WDT1 Bit 0 WDT0
Address: '7'hex - Subaddress: 'A'hex Reset value: 1111b
Bit 3 = MSB, Bit 0 = LSB
WDL WatchDog Lock mode WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no effect. After the WDL-bit is cleared, the watchdog is active until a system reset or power-on reset occurs. WatchDog Run and stop mode WDR = 1, the watchdog is stopped/disabled WDR = 0, the watchdog is active/enabled WatchDog Time 1 WatchDog Time 0
WDR
WDT1 WDT0
Both these bits control the time interval for the watchdog reset
Table 14. Watchdog Time Control Bits
WDT1 0 0 1 1 Note: WDT0 0 1 0 1 Divider 512 2048 16384 131072 Delay Time to Reset with tin = 1/(2/1 MHz) 0.256 ms/0.512 ms 1.024 ms/2.048 ms 8.2 ms/16.4 ms 65.5 ms/131 ms
tin: input clock period = 1/Cin (see Figure 14 on page 14)
Timer 2
8-/12 Bit Timer for:
* * * * Interrupt, square-wave, pulse and duty cycle generation Baud rate generation for the internal shift register Manchester and Bi-phase modulation together with the SSI Carrier frequency generation and modulation together with the SSI
Timer 2 can be used as an interval timer for interrupt generation, as signal generator or as baud rate generator and modulator for the serial interface. It consists of a 4-bit and an 8-bit up counter stage which both have compare registers. The 4-bit counter stages of Timer 2 are cascadable as a 12-bit timer or as an 8-bit timer with a 4-bit prescaler. The timer can also be configured as an 8-bit timer and a separate 4-bit prescaler. The Timer 2 input can be supplied via the system clock, the external input clock (T2I), the Timer 1 output clock or the shift clock of the serial interface. The external input clock T2I is not synchronized with SYSCL. Therefore, it is possible to use Timer 2 with a higher clock speed than SYSCL. Furthermore; with that input clock Timer 2 operates in the power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes) as well as in the POWER-DOWN (CPU core -> sleep and OSC-Stop -> no). All other clock sources supplied no clock signal in SLEEP. The 4-bit counter stages of Timer 2 have an additional clock output (POUT).
28
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Its output has a modulator stage that allows the generation of pulses as well as the generation and modulation of carrier frequencies. Timer 2 output can modulate with the shift register internal data output to generate Bi-phase- or Manchester-code. If the serial interface is used to modulate a bit-stream, the 4-bit stage of Timer 2 has a special task. The shift register can only handle bit-stream lengths divisible by 8. For other lengths, the 4-bit counter stage can be used to stop the modulator after the right bit-count is shifted out. If the timer is used for carrier frequency modulation, the 4-bit stage works together with an additional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier frequency and duty cycle. The 8-bit counter is used to enable and disable the modulator output for a programmable count of pulses. The timer has a 4-bit and an 8-bit compare register for programming the time interval, t. For programming the timer function, it has four mode and control registers. The comparator output of stage 2 is controlled by a special compare mode register (T2CM). This register contains mask bits for the actions (counter reset, output toggle, timer interrupt) which can be triggered by a compare match event or the counter overflow. This architecture enables the timer function for various modes. Timer 2 compare data values. Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit compare register (T2CO2). Both these compare registers are cascadable as a 12-bit compare register, or 8-bit compare register and 4-bit compare register. For 12-bit compare data value: For 8-bit compare data value: For 4-bit compare data value: m = x +1 n = y +1 l = z +1 0 x 4095 0 y 255 0 z 15
Figure 26. Timer 2
I/O-bus
P4CR
T2I
T2M1
T2M2
DCGO
SYSCL T1OUT SCL CL2/1
4-bit Counter 2/1
RES OVF1 POUT
CL2/2
T2O
DCG
8-bit Counter 2/2
RES OVF2 TOG2
OUTPUT
M2 MOUT
T2C
Compare 2/1
CM1
Control
Compare 2/2
INT4
to Modulator 3
T2CO1
SSI POUT
T2CM
T2CO2
Bi-phase Manchester Modulator
Timer 2 modulator output-stage
SO I/O-bus SSI
Control
SSI
29
4708C-4BMCU-02/04
Timer 2 Modes
Mode 1: 12-bit Compare Counter
The 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. A compare match signal of the 4-bit and the 8-bit stage generates the signal for the counter reset, toggle flip-flop or interrupt. The compare action is programmable via the compare mode register (T2CM). The 4-bit counter overflow (OVF1) supplies the clock output (POUT) with clocks. The duty cycle generator (DCG) has to be bypassed in this mode.
Figure 27. 12-bit Compare Counter
POUT (CL2/1 /16) CL2/1 OVF2 TOG2 RES INT4
4-bit counter
RES
DCG
8-bit counter
4-bit compare
CM1
8-bit compare
CM2 Timer 2 output mode and T2OTM-bit
4-bit register
T2D1, 0
8-bit register
T2RM
T2OTM
T2IM
T2CTM
Mode 2: 8-bit Compare Counter with 4-bit Programmable Prescaler
The 4-bit stage is used as a programmable prescaler for the 8-bit counter stage. In this mode, a duty cycle stage is also available. This stage can be used as an additional 2-bit prescaler or for generating duty cycles of 25%, 33% and 50%. The 4-bit compare output (CM1) supplies the clock output (POUT) with clocks.
Figure 28. 8-bit Compare Counter
DCGO POUT CL2/1 OVF2 TOG2 RES INT4
4-bit counter
RES
DCG
8-bit counter
4-bit compare
CM1
8-bit compare
CM2 Timer 2 output mode and T2OTM-bit
4-bit register
T2D1, 0
8-bit register
T2RM
T2OTM
T2IM
T2CTM
Mode 3/4: 8-bit Compare Counter and 4-bit Programmable Prescaler
In these modes the 4-bit and the 8-bit counter stages work independently as a 4-bit prescaler and an 8-bit timer with a 2-bit prescaler or as a duty cycle generator. Only in mode 3 and mode 4 can the 8-bit counter be supplied via the external clock input (T2I) which is selected via the P4CR register. The 4-bit prescaler is started by activating mode 3 and stopped and reset in mode 4. Changing mode 3 and 4 has no effect for the 8-bit timer stage. The 4-bit stage can be used as a prescaler for the SSI or to generate the stop signal for modulator 2.
30
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Figure 29. 4-/8-bit Compare Counter
DCGO T2I SYSCL CL2/2
DCG
8-bit counter
OVF2 TOG2
RES INT4 CM2 Timer 2 output mode and T2OTM-bit P4CR P41M2, 1 T2D1, 0
8-bit compare
8-bit register
T2RM
T2OTM
T2IM
T2CTM
T1OUT SYSCL SCL
MUX
CL2/1
4-bit counter
RES CM1 POUT
4-bit compare
T2CS1, 0
4-bit register
Timer 2 Output Modes
The signal at the timer output is generated via Modulator 2. In the toggle mode, the compare match event toggles the output T2O. For high resolution duty cycle modulation 8 bits or 12 bits can be used to toggle the output. In the duty cycle burst modulator modes the DCG output is connected to T2O and switched on and off either by the toggle flipflop output or the serial data line of the SSI. Modulator 2 also has 2 modes to output the content of the serial interface as Bi-phase or Manchester code. The modulator output stage can be configured by the output control bits in the T2M2 register. The modulator is started with the start of the shift register (SIR = 0) and stopped either by carrying out a shift register stop (SIR = 1) or compare match event of stage 1 (CM1) of Timer 2. For this task, Timer 2 mode 3 must be used and the prescaler has to be supplied with the internal shift clock (SCL).
Figure 30. Timer 2 Modulator Output Stage
DCGO SO TOG2 RE Bi-phase/ Manchester modulator Toggle S1 RES/SET M2 S3 S2 T2O
SSI CONTROL
FE
OMSK T2M2 T2OS2, 1, 0 T2TOP
M2
31
4708C-4BMCU-02/04
Timer 2 Output Signals
Timer 2 Output Mode 1 Toggle Mode A: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O Figure 31. Interrupt Timer/Square Wave Generator -- Output Toggles with Each Edge Compare Match Event
Input Counter 2 T2R
0 0 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1
Counter 2 CMx INT4 T2O
Toggle Mode B: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O Figure 32. Pulse Generator -- Timer Output Toggles with Timer Start If T2TS-Bit is Set
Input Counter 2 T2R
0 0 0 1 2 3 4 5 6 7 4095/ 255 0 1 2 3 4 5 6
Counter 2 CMx INT4 T2O
Toggle by start
T2O
Timer 2 Output Mode 1 Toggle Mode C: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O Figure 33. Pulse Generator -- Timer Toggles with Timer Overflow and Compare Match
Input Counter 2 T2R
0 0 0 1 2 3 4 5 6 7 4095/ 255 0 1 2 3 4 5 6
Counter 2 CMx OVF2 INT4 T2O
32
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Timer 2 Output Mode 2 Duty Cycle Burst Generator 1: The DCG output signal (DCGO) is given to the output, and gated by the output flip-flop (M2) Figure 34. Carrier Frequency Burst Modulation with Timer 2 Toggle Flip-Flop Output
DCGO
1 2 0 1 2 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5
Counter 2 TOG2 M2 T2O
Counter = compare register (=2)
Timer 2 Output Mode 3 Duty Cycle Burst Generator 2: The DCG output signal (DCGO) is given to the output, and gated by the SSI internal data output (SO) Figure 35. Carrier Frequency Burst Modulation with SSI Data Output
DCGO
1201201201201201201201201201201201201201
Counter 2
Counter = compare register (=2)
TOG2 SO T2O
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13
Timer 2 Output Mode 4 Bi-phase Modulator: Timer 2 modulates the SSI internal data output (SO) to Bi-phase code. Figure 36. Bi-phase Modulation
TOG2 SC
8-bit SR-Data
SO T2O
0 Bit 7 0 Data: 00110101
0
1
1
0
1
0
1 Bit 0
0
1
1
0
1
0
1
33
4708C-4BMCU-02/04
Timer 2 Output Mode 5 Manchester Modulator: Timer 2 modulates the SSI internal data output (SO) to Manchester code. Figure 37. Manchester Modulation
TOG2 SC
8-bit SR-Data
SO T2O
0
0 Bit 7 0
0
1
1
0
1
0
1 Bit 0
1
1
0
1
0
1 Bit 0
Bit 7 Data: 00110101
Timer 2 Output Mode 7 PWM Mode: Pulse-width modulation output on Timer 2 output pin (T2O)
In this mode the timer overflow defines the period and the compare register defines the duty cycle. During one period only the first compare match occurrence is used to toggle the timer output flip-flop, until overflow occur all further compare match are ignored. This avoids the situation that changing the compare register causes the occurrence of several compare match during one period. The resolution at the pulse-width modulation Timer 2 mode 1 is 12-bit and all other Timer 2 modes are 8-bit.
Figure 38. PWM Modulation
Input clock Counter 2/2 T2R
0 0 50 255 0 100 255 0 150 255 0 50 255 0 100
Counter 2/2 CM2 OVF2 INT4 T2O
T1 T load the next compare value T2CO2=150 load load
T2 T
T3 T
T1 T
T2
T
Timer 2 Registers
Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and its output function. All registers are indirectly addressed using extended addressing as described in section "Addressing Peripherals". The alternate functions of the Ports BP41 or BP42 must be selected with the Port 4 control register P4CR, if one of the Timer 2 modes require an input at T2I/BP41 or an output at T2O/BP42.
34
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Timer 2 Control Register (T2C)
Address: '7'hex - Subaddress: '0'hex Bit 3 T2C T2CS1 Bit 2 T2CS0 Bit 1 T2TS Bit 0 T2R Reset value: 0000b
T2CS1 T2CS0
Timer 2 Clock Select bit 1 Timer 2 Clock Select bit 0
Table 15. Timer 2 Clock Select Bits
T2CS1 0 0 1 1 T2CS0 0 1 0 1 Input Clock (CL 2/1) of Counter Stage 2/1 System clock (SYSCL) Output signal of Timer 1 (T1OUT) Internal shift clock of SSI (SCL) Reserved
T2TS
Timer 2 Toggle with Start T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with T2R Timer 2 Run T2R = 0, Timer 2 stop and reset T2R = 1, Timer 2 run
T2R
Timer 2 Mode Register 1 (T2M1)
Address: '7'hex - Subaddress: '1'hex Bit 3 T2M1 T2D1 Bit 2 T2D0 Bit 1 T2MS1 Bit 0 T2MS0 Reset value: 1111b
T2D1 T2D0
Timer 2 Duty cycle bit 1 Timer 2 Duty cycle bit 0
Table 16. Timer 2 Duty Cycle Bits
T2D1 1 1 0 T2MS1 T2MS0 T2D0 1 0 1 Timer 2 Mode Select bit 1 Timer 2 Mode Select bit 0 Function of Duty Cycle Generator (DCG) Bypassed (DCGO0) Duty cycle 1/1 (DCGO1) Duty cycle 1/2 (DCGO2) Additional Divider Effect /1 /2 /3
35
4708C-4BMCU-02/04
Table 17. Timer 2 Mode Select Bits
Mode 1 T2MS1 1 T2MS0 1 Clock Output (POUT) Timer 2 Modes
12-bit compare counter, the 4-bit counter overflow (OVF1) DCG have to be bypassed in this mode 8-bit compare counter with 4-bit programmable prescaler and duty cycle generator 8-bit compare counter clocked by SYSCL or the external clock input T2I, 4bit prescaler run, the counter 2/1 starts after writing mode 3 8-bit compare counter clocked by SYSCL or the external clock input T2I, 4bit prescaler stop and resets
2
1
0
4-bit compare output (CM1)
3
0
1
4-bit compare output (CM1)
4
0
0
4-bit compare output (CM1)
Duty Cycle Generator
The duty cycle generator generates duty cycles from 25%, 33% or 50%. The frequency at the duty cycle generator output depends on the duty cycle and the Timer 2 prescaler setting. The DCG-stage can also be used as an additional programmable prescaler for Timer 2.
Figure 39. DCG Output Signals
DCGIN DCGO0 DCGO1 DCGO2 DCGO3
36
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Timer 2 Mode Register 2 (T2M2)
Address: '7'hex - Subaddress: '2'hex Bit 3 T2M2 T2TOP T2TOP Bit 2 T2OS2 Bit 1 T2OS1 Bit 0 T2OS0 Reset value: 1111b
Timer 2 Toggle Output Preset This bit allows the programmer to preset the Timer 2 output T2O. T2TOP = 0, resets the toggle outputs with the write cycle (M2 = 0) T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1) Note: If T2R = 1, no output preset is possible Timer 2 Output Select bit 2 Timer 2 Output Select bit 1 Timer 2 Output Select bit 0
T2OS2 T2OS1 T2OS0
Table 18. Timer 2 Output Select Bits
Output Mode 1 T2OS2 1 T2MS1 1 T2MS0 1 Clock Output (POUT) Toggle mode: a Timer 2 compare match toggles the output flip-flop (M2) -> T2O Duty cycle burst generator 1: the DCG output signal (DCG0) is given to the output and gated by the output flip-flop (M2) Duty cycle burst generator 2: the DCG output signal (DCGO) is given to the output and gated by the SSI internal data output (SO) Bi-phase modulator: Timer 2 modulates the SSI internal data output (SO) to Bi-phase code Manchester modulator: Timer 2 modulates the SSI internal data output (SO) to Manchester code SSI output: T2O is used directly as SSI internal data output (SO) PWM mode: an 8/12-bit PWM mode Not allowed
2
1
1
0
3
1
0
1
4
1
0
0
5
0
1
1
6 7 8 Note:
0 0 0
1 0 0
0 1 0
If one of these output modes is used the T2O alternate function of Port 4 must also be activated.
Timer 2 Compare and Compare Mode Registers
Timer 2 has two separate compare registers, T2CO1 for the 4-bit stage and T2CO2 for the 8-bit stage of Timer 2. The timer compares the contents of the compare register current counter value and if it matches it generates an output signal. Depending on the timer mode, this signal is used to generate a timer interrupt, to toggle the output flip-flop as SSI clock or as a clock for the next counter stage. In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit compare value. In all other modes, the two compare registers work independently as a 4-bit and 8-bit compare register. When assigned to the compare register a compare event will be suppressed.
37
4708C-4BMCU-02/04
Timer 2 Compare Mode Register (T2CM)
Bit 3 T2CM T2OTM T2OTM Bit 2 T2CTM Bit 1 T2RM Bit 0 T2IM
Address: '7'hex - Subaddress: '3'hex Reset value: 0000b
Timer 2 Overflow Toggle Mask bit T2OTM = 0, disable overflow toggle T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles the output flip-flop (TOG2). If the T2OTM-bit is set, only a counter overflow can generate an interrupt except on the Timer 2 output mode 7. Timer 2 Compare Toggle Mask bit T2CTM = 0, disable compare toggle T2CTM = 1, enable compare toggle, a match of the counter with the compare register toggles output flip-flop (TOG2). In Timer 2 output mode 7 and when the T2CTM-bit is set, only a match of the counter with the compare register can generate an interrupt. Timer 2 Reset Mask bit T2RM = 0, disable counter reset T2RM = 1, enable counter reset, a match of the counter with the compare register resets the counter Timer 2 Interrupt Mask bit T2IM = 0, disable Timer 2 interrupt T2IM = 1, enable Timer 2 interrupt
T2CTM
T2RM
T2IM
Table 19. Timer 2 Toggle Mask Bits
Timer 2 Output Mode 1, 2, 3, 4, 5 and 6 1, 2, 3, 4, 5 and 6 7 T2OTM 0 1 x T2CTM x x 1 Timer 2 Interrupt Source Compare match (CM2) Overflow (OVF2) Compare match (CM2)
Timer 2 COmpare Register 1 (T2CO1)
T2CO1 Write cycle Bit 3 Bit 2
Address: '7'hex - Subaddress: '4'hex Bit 1 Bit 0 Reset value: 1111b
In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.
Timer 2 COmpare Register 2 (T2CO2) Byte Write
T2CO2 First write cycle Second write cycle
Bit 3 Bit 7 Bit 2 Bit 6
Address: '7'hex - Subaddress: '5'hex
Bit 1 Bit 5 Bit 0 Bit 4
Reset value: 1111b Reset value: 1111b
38
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Synchronous Serial Interface (SSI) SSI Features
* - - - - - - 2- and 3-wire NRZ 2-wire mode Bi-phase modulation Manchester modulation Pulse-width demodulation Burst modulation
With Timer 2:
SSI Peripheral Configuration
The synchronous serial interface (SSI) can be used either for serial communication with external devices such as EEPROMs, shift registers, display drivers, other microcontrollers, or as a means for generating and capturing on-chip serial streams of data. External data communication takes place via Port 4's (BP4) multi-functional port which can be software configured by writing the appropriate control word into the P4CR register. The SSI can be configured in any one of the following ways: 1. 2-wire external interface for bi-directional data communication with one data terminal and one shift clock. The SSI uses Port BP43 as a bi-directional serial data line (SD) and BP40 as a shift clock line (SC). 2. 3-wire external interface for simultaneous input and output of serial data, with a serial input data terminal (SI), a serial output data terminal (SO) and a shift clock (SC). The SSI uses BP40 as a shift clock (SC), while the serial data input (SI) is applied to BP43 (configured in P4CR as input). Serial output data (SO) in this case is passed through to BP42 (configured in P4CR to T2O) via Timer 2 output stage (T2M2 configured in mode 6). 3. Timer/SSI combined modes - the SSI used together with Timer 2 is capable of performing a variety of data modulation and functions (see section ''Timer''). The modulating data is converted by the SSI into a continuous serial stream of data which is in turn modulated in one of the timer functional blocks.
Figure 40. Block Diagram of the Synchronous Serial Interface
I/O-bus Timer 2
SIC1 SIC2 SISC
SO Control SC SSI-Control INT3
SI SCI SC
TOG2 POUT T1OUT SYSCL
SO /2
Shift_CL
Output 8-bit Shift Register SI LSB SD
MSB
STB
SRB
Transmit Buffer I/O-bus
Receive Buffer
39
4708C-4BMCU-02/04
General SSI Operation
The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit buffers - the receive buffer (SRB) for capturing the incoming serial data and a transmit buffer (STB) for intermediate storage of data to be serially output. Both buffers are directly accessable by software. Transferring the parallel buffer data into and out of the shift register is controlled automatically by the SSI control, so that both single byte transfers or continuous bit streams can be supported. The SSI can generate the shift clock (SC) either from one of several on-chip clock sources or accept an external clock. The external shift clock is output on, or applied to the Port BP40. Selection of an external clock source is performed by the Serial Clock Direction control bit (SCD). In the combinational modes, the required clock is selected by the corresponding timer mode. The SSI can operate in three data transfer modes - synchronous 8-bit shift mode, a 9-bit Multi-Chip Link mode (MCL), containing 8-bit data and 1-bit acknowledge, and a corresponding 8-bit MCL mode without acknowledge. In both MCL modes the data transmission begins after a valid start condition and ends with a valid stop condition. External SSI clocking is not supported in these modes. The SSI should thus generate and have full control over the shift clock so that it can always be regarded as an MCL-bus master device. All directional control of the external data port used by the SSI is handled automatically and is dependent on the transmission direction set by the Serial Data Direction (SDD) control bit. This control bit defines whether the SSI is currently operating in transmit (TX) mode or receive (RX) mode. Serial data is organized in 8-bit telegrams which are shifted with the most significant bit first. In the 9-bit MCL mode, an additional acknowledge bit is appended to the end of the telegram for handshaking purposes (see ''MCL protocol''). At the beginning of every telegram, the SSI control loads the transmit buffer into the shift register and proceeds immediately to shift data serially out. At the same time, incoming data is shifted into the shift register input. This incoming data is automatically loaded into the receive buffer when the complete telegram has been received. Data can, if required thus be simultaneously received and transmitted. Before data can be transferred, the SSI must first be activated. This is performed by means of the SSI reset control (SIR) bit. All further operation then depends on the data directional mode (TX/RX) and the present status of the SSI buffer registers shown by the Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates the (empty/full) status of either the transmit buffer (in TX mode), or the receive buffer (in RX mode). The control logic ensures that data shifting is temporarily halted at any time, if the appropriate receive/transmit buffer is not ready (SRDY = 0). The SRDY status will then automatically be set back to '1' and data shifting resumed as soon as the application software loads the new data into the transmit register (in TX mode) or frees the shift register by reading it into the receive buffer (in RX mode). A further activity status (ACT) bit indicates the present status of serial communication. The ACT bit remains high for the duration of the serial telegram or if MCL stop or start conditions are currently being generated. Both the current SRDY and ACT status can be read in the SSI status register. To deactivate the SSI, the SIR bit must be set high.
40
ATA6020N
4708C-4BMCU-02/04
ATA6020N
8-bit Synchronous Mode Figure 41. 8-bit Synchronous Mode
SC (rising edge) SC (falling edge) DATA 0 Bit 7 SD/TO2 0 Bit 7 Data: 00110101 0 1 1 0 1 0 0 1 1 0 1 0 1 Bit 0 1 Bit 0
In the 8-bit synchronous mode, the SSI can operate as either a 2- or 3-wire interface (see ''SSI Peripheral Configuration''). The serial data (SD) is received or transmitted in NRZ format, synchronized to either the rising or falling edge of the shift clock (SC). The choice of clock edge is defined by the Serial Mode Control bits (SM0, SM1). It should be noted that the transmission edge refers to the SC clock edge with which the SD changes. To avoid clock skew problems, the incoming serial input data is shifted in with the opposite edge. When used together with one of the timer modulator or demodulator stages, the SSI must be set in the 8-bit synchronous mode 1. In RX mode, as soon as the SSI is activated (SIR = 0), 8 shift clocks are generated and the incoming serial data is shifted into the shift register. This first telegram is automatically transferred into the receive buffer and the SRDY flag is set to 0 indicating that the receive buffer contains valid data. At the same time an interrupt (if enabled) is generated. The SSI then continues shifting in the following 8-bit telegram. If, during this time the first telegram has been read by the controller, the second telegram will also be transferred in the same way into the receive buffer and the SSI will continue clocking in the next telegram. Should, however, the first telegram not have been read (SRDY = 1), then the SSI will stop, temporarily holding the second telegram in the shift register until a certain point in time when the controller is able to service the receive buffer. In this way no data is lost or overwritten. Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and latch the present contents of the shift register into the receive buffer. This can be used for clocking in a data telegram of less than 8 bits in length. Care should be taken to read out the final complete 8-bit data telegram of a multiple word message before deactivating the SSI (SIR = 1) and terminating the reception. After termination, the shift register contents will overwrite the receive buffer.
41
4708C-4BMCU-02/04
Figure 42. Example of 8-bit Synchronous Transmit Operation
SC msb SD tx data 1 SIR lsb
0
msb tx data 2
lsb msb tx data 3
lsb
0
7654321
765432107654321
SRDY
ACT Interrupt (IFN = 0) Interrupt (IFN = 1) Write STB (tx data 1) Write STB (tx data 2) Write STB (tx data 3)
Figure 43. Example of 8-bit Synchronous Receive Operation
SC msb SD lsb msb lsb msb lsb
7654321076543210 rx data 1 rx data 2
765432107654 rx data 3
SIR
SRDY
ACT Interrupt (IFN = 0) Interrupt (IFN = 1) Read SRB (rx data 1) Read SRB (rx data 2) Read SRB (rx data 3)
9-bit Shift Mode
In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It always operates as an MCL master device, i.e., SC is always generated and output by the SSI. Both the MCL start and stop conditions are automatically generated whenever the SSI is activated or deactivated by the SIR-bit. In accordance with the MCL protocol, the output data is always changed in the clock low phase and shifted in on the high phase. Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate data direction for the first word must be set using the SDD control bit. The state of this bit controls the direction of the data port (BP43 or MCL_SD). Once started, the 8 data bits are, depending on the selected direction, either clocked into or out of the shift register. During the 9th clock period, the port direction is automatically switched over so that the corresponding acknowledge bit can be shifted out or read in. In transmit mode, the acknowledge bit received from the device is captured in the SSI Status Register (TACK) where it can be read by the controller. A receive mode, the state of the acknowledge bit to be returned to the device is predetermined by the SSI Status Register (RACK).
42
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Changing the directional mode (TX/RX) should not be performed during the transfer of an MCL telegram. One should wait until the end of the telegram which can be detected using the SSI interrupt (IFN = 1) or by interrogating the ACT status. A 9-bit telegram, once started will always run to completion and will not be prematurely terminated by the SIR bit. So, if the SIR-bit is set to '1' in with telegram, the SSI will complete the current transfer and terminate the dialog with an MCL stop condition.
Figure 44. Example of MCL Transmit Dialog
Start SC msb SD lsb msb lsb Stop
76543210A tx data 1
76543210A tx data 2
SRDY
ACT Interrupt (IFN = 0) Interrupt (IFN = 1) SIR SDD Write STB (tx data 1) Write STB (tx data 2)
Figure 45. Example of MCL Receive Dialog
Start SC msb SD lsb msb lsb Stop
76543210A tx data 1
76543210A rx data 2
SRDY
ACT Interrupt (IFN = 0) Interrupt (IFN = 1) SIR SDD
Write STB (tx data 1)
Read SRB (rx data 2)
43
4708C-4BMCU-02/04
8-bit Pseudo MCL Mode
In this mode, the SSI exhibits all the typical MCL operational features except for the acknowledge-bit which is never expected or transmitted. The MCL protocol constitutes a simple 2-wire bi-directional communication highway via which devices can communicate control and data information. Although the MCL protocol can support multi-master bus configurations, the SSI, in MCL mode is intended for use purely as a master controller on a single master bus system. So all reference to multiple bus control and bus contention will be omitted at this point. All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit. Normally the communication channel is opened with a so-called start condition, which initializes all devices connected to the bus. This is then followed by a data telegram, transmitted by the master controller device. This telegram usually contains an 8-bit address code to activate a single slave device connected onto the MCL bus. Each slave receives this address and compares it with its own unique address. The addressed slave device, if ready to receive data will respond by pulling the SD line low during the 9th clock pulse. This represents a so-called MCL acknowledge. The controller on detecting this affirmative acknowledge then opens a connection to the required slave. Data can then be passed back and forth by the master controller, each 8-bit telegram being acknowledged by the respective recipient. The communication is finally closed by the master device and the slave device put back into standby by applying a stop condition onto the bus.
MCL Bus Protocol
Figure 46. MCL Bus Protocol 1
(1) (2) SC (4) (4) (3) (1)
SD
Start condition
Data valid
Data change
Data valid
Stop condition
Bus not busy (1) Start data transfer (2) Stop data transfer (3) Data valid (4)
Both data and clock lines remain HIGH. A HIGH to LOW transition of the SD line while the clock (SC) is HIGH defines a START condition. A LOW to HIGH transition of the SD line while the clock (SC) is HIGH defines a STOP condition. The state of the data line represents valid data when, after START condition, the data line is stable for the duration of the HIGH period of the clock signal. All address and data words are serially transmitted to and from the device in eight-bit words. The receiving device returns a zero on the data line during the ninth clock cycle to acknowledge word receipt.
Acknowledge
44
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Figure 47. MCL Bus Protocol 2
SC 1 n 8 9
SD
Start
1st Bit
8th Bit
ACK
Stop
SSI Interrupt
The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e., transmit buffer empty or receive buffer full) at the end of an SSI data telegram or on the falling edge of the SC/SD pins on Port 4 (see P4CR). SSI interrupt selection is performed by the Interrupt Function control bit (IFN). The SSI interrupt is usually used to synchronize the software control of the SSI and inform the controller of the present SSI status. Port 4 interrupts can be used together with the SSI or, if the SSI itself is not required, as additional external interrupt sources. In either case this interrupt is capable of waking the controller out of sleep mode. To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and the Interrupt Function (IFN) while Port 4 interrupts are enabled by setting appropriate control bits in P4CR register.
Modulation
If the shift register is used together with Timer 2 for modulation purposes, the 8-bit synchronous mode must be used. In this case, the unused Port 4 pins can be used as conventional bi-directional ports. The modulation stage, if enabled, operates as soon as the SSI is activated (SIR = 0) and ceases when deactivated (SIR = 1). Due to the byte-orientated data control, the SSI (when running normally) generates serial bit-streams which are submultiples of 8 bits. However, an SSI output masking (OMSK) function permits, however, the generation of bit-streams of any length. The OMSK signal is derived indirectly from the 4-bit prescaler of the Timer 2 and masks out a programmable number of unrequired trailing data bits during the shifting out of the final data word in the bit stream. The number of non-masked data bits is defined by the value pre-programmed in the prescaler compare register. To use output masking, the modulator stop mode bit (MSM) must be set to '0' before programming the final data word into the SSI transmit buffer. This in turn, enables shift clocks to the prescaler when this final word is shifted out. On reaching the compare value, the prescaler triggers the OMSK signal and all following data bits are blanked.
45
4708C-4BMCU-02/04
Figure 48. SSI Output Masking Function
Timer 2
CL2/1 SCL Compare 2/1 CM1 OMSK Control SC SSI-control Output TOG2 POUT T1OUT SYSCL SO /2 Shift_CL MSB 8-bit shift register SI LSB SO
4-bit counter 2/1
Serial Interface Registers Serial Interface Control Register 1 (SIC1)
Bit 3 SIC1 SIR Bit 2 SCD Bit 1 SCS1 Bit 0 SCS0 Reset value: 1111b
Auxiliary register address: '9'hex
SIR
Serial Interface Reset SIR = 1, SSI inactive SIR = 0, SSI active Serial Clock Direction SCD = 1, SC line used as output SCD = 0, SC line used as input Note: This bit has to be set to '1' during the MCL mode
SCD
SCS1 SCS0
Serial Clock source Select bit 1 Serial Clock source Select bit 0 Note: with SCD = '0' the bits SCS1 and SCS0 are insignificant
Table 20. Serial Clock Source Select Bits
SCS1 1 1 0 0 SCS0 1 0 1 0 Internal Clock for SSI SYSCL/2 T1OUT/2 POUT/2 TOG2/2
46
ATA6020N
4708C-4BMCU-02/04
ATA6020N
* * * In transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY = 1). Setting SIR-bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only). In MCL modes, writing a 0 to SIR generates a start condition and writing a 1 generates a stop condition.
Serial Interface Control Register 2 (SIC2)
Bit 3 SIC2 MSM MSM Bit 2 SM1 Bit 1 SM0 Bit 0 SDD
Auxiliary register address: 'A'hex Reset value: 1111b
Modular Stop Mode MSM = 1, modulator stop mode disabled (output masking off) MSM = 0, modulator stop mode enabled (output masking on) - used in modulation modes for generating bit streams which are not sub-multiples of 8 bit.
SM1 SM0
Serial Mode control bit 1 Serial Mode control bit 0
Table 21. Serial Mode Control Bits
Mode 1 2 3 4 SM1 1 1 0 0 SM0 1 0 1 0 SSI Mode 8-bit NRZ-Data changes with the rising edge of SC 8-bit NRZ-Data changes with the falling edge of SC 9-bit two-wire MCL compatible 8-bit two-wire pseudo MCL compatible (no acknowledge)
SDD
Serial Data Direction SDD = 1, transmit mode - SD line used as output (transmit data). SRDY is set by a transmit buffer write access SDD = 0, receive mode - SD line used as input (receive data). SRDY is set by a receive buffer read access
SDD controls port directional control and defines the reset function for the SRDY-flag
47
4708C-4BMCU-02/04
Serial Interface Status and Control Register (SISC)
Bit 3 SISC SISC write read - Bit 2 RACK TACK Bit 1 SIM ACT Bit 0 IFN SRDY
Primary register address: 'A'hex Reset value: 1111b Reset value: xxxxb
RACK
Receive ACKnowledge status/control bit for MCL mode RACK = 0, transmit acknowledge in next receive telegram RACK = 1, transmit no acknowledge in last receive telegram Transmit ACKnowledge status/control bit for MCL mode TACK = 0, acknowledge received in last transmit telegram TACK = 1, no acknowledge received in last transmit telegram Serial Interrupt Mask SIM = 1, disable interrupts SIM = 0, enable serial interrupt. An interrupt is generated. Interrupt FuNction IFN = 1, the serial interrupt is generated at the end of the telegram IFN = 0, the serial interrupt is generated when the SRDY goes low (i.e., buffer becomes empty/full in transmit/receive mode) Serial interface buffer ReaDY status flag SRDY = 1, in receive mode: receive buffer empty in transmit mode: transmit buffer full SRDY = 0, in receive mode: receive buffer full in transmit mode: transmit buffer empty Transmission ACTive status flag ACT = 1, transmission is active, i.e., serial data transfer. Stop or start conditions are currently in progress. ACT = 0, transmission is inactive
TACK
SIM
IFN
SRDY
ACT
Serial Transmit Buffer (STB) - Byte Write
STB First write cycle Second write cycle Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5
Primary register address: '9'hex Bit 0 Bit 4 Reset value: xxxxb Reset value: xxxxb
The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift register and starts shifting with the most significant bit.
Serial Receive Buffer (SRB) - Byte Read
SRB First read cycle Second read cycle Bit 7 Bit 3 Bit 6 Bit 2 Bit 5 Bit 1
Primary register address: '9'hex Bit 4 Bit 0 Reset value: xxxxb Reset value: xxxxb
The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant bit first) and loads content into the receive buffer when complete telegram has been received.
48
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Combination Modes
The UTCM consists of one timer (Timer 2) and a serial interface. There is a multitude of modes in which the timers and serial interface can work together. The 8-bit wide serial interface operates as shift register for modulation. The modulator units work together with the timers and shift the data bits into or out of the shift register.
Combination Mode Timer 2 and SSI Figure 49. Combination Timer 2 and SSI
I/O-bus
P4CR
T2I
T2M1
T2M2
DCGO SYSCL T1OUT reserved SCL CL2/1 4-bit Counter 2/1 RES OVF1 POUT CL2/2 T2O
DCG
8-bit Counter 2/2 RES OVF2 TOG2
OUTPUT
T2C
Compare 2/1
POUT
Timer 2 - control
CM1
Compare 2/2
INT4
MOUT Bi-phase Manchester Modulator
T2CO1
TOG2
T2CM
T2CO2
SO
Timer 2 modulator output-stage
Control
I/O-bus
SIC1
TOG2 POUT T1OUT SYSCL SCLI
SIC2
SISC
Control INT3 SO SC
SSI-control
Output
SO SI Shift_CL MSB
SCL
8-bit shift register
SD
LSB
STB
Transmit buffer I/O-bus
SRB
Receive buffer
49
4708C-4BMCU-02/04
Combination Mode 1 Burst Modulation
SSI mode 1: Timer 2 mode 1, 2, 3 or 4: Timer 2 output mode 3: 8-bit NRZ and internal data SO output to the Timer 2 modulator stage 8-bit compare counter with 4-bit programmable prescaler and DCG Duty cycle burst generator
Figure 50. Carrier Frequency Burst Modulation with the SSI Internal Data Output
DCGO
1201201201201201201201201201201201201201
Counter 2
Counter = compare register (=2)
TOG2 SO T2O
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13
Combination Mode 2: Bi-phase Modulation 1
SSI mode 1: Timer 2 mode 1, 2, 3 or 4: Timer 2 output mode 4: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage 8-bit compare counter with 4-bit programmable prescaler The Modulator 2 of Timer 2 modulates the SSI internal data out put to Bi-phase code
Figure 51. Bi-phase Modulation 1
TOG2 SC
8-bit SR-data
SO T2O
0 Bit 7 0 Data: 00110101
0
1
1
0
1
0
1 Bit 0
0
1
1
0
1
0
1
50
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Combination Mode 3: Manchester Modulation 1
SSI mode 1: Timer 2 mode 1, 2, 3 or 4: Timer 2 output mode 5: 8-bit shift register internal data output (SO) to Timer 2 modulator stage 8-bit compare counter with 4-bit programmable prescaler The Modulator 2 of Timer 2 modulates the SSI internal data out put to Manchester code
Figure 52. Manchester Modulation 1
TOG2 SC
8-bit SR-data
SO T2O
0
0 Bit 7 0
0
1
1
0
1
0
1 Bit 0
1
1
0
1
0
1 Bit 0
Bit 7 Data: 00110101
Combination Mode 4: Manchester Modulation 2
SSI mode 1: Timer 2 mode 3: Timer 2 output mode 5: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage 8-bit compare counter and 4-bit prescaler The Modulator 2 of Timer 2 modulates the SSI data output to Manchester code
The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI has a special mode to supply the prescaler with the shift-clock. The control output signal (OMSK) of the SSI is used as stop signal for the modulator. Figure 53 is an example for a 12-bit Manchester telegram.
Figure 53. Manchester Modulation 2
SCLI Buffer full SIR SO SC MSM Timer 2 Mode 3 SCL Counter 2/1 OMSK T2O 0 0 0 0 0 Counter 2/1 = Compare Register 2/1 (= 4) 0 0 0 0 1 2 3 4 0 1 2 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
51
4708C-4BMCU-02/04
Combination Mode 5: Bi-phase Modulation 2
SSI mode 1: Timer 2 mode 3: Timer 2 output mode 4: 8-bit shift register internal data output (SO) to Timer 2 modulator stage 8-bit compare counter and 4-bit prescaler The modulator 2 of Timer 2 modulates the SSI data output to Bi-phase code
The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for Modulator 2. The SSI has a special mode to supply the prescaler via the shift-clock. The control output signal (OMSK) of the SSI is used as a stop signal for the modulator. Figure 54 is an example for a 13-bit Bi-phase telegram.
Figure 54. Bi-phase Modulation
SCLI Buffer full SIR SO SC MSM Timer 2 Mode 3 SCL 2/1 OMSK T2O 0 0 0 0 0 Counter 2/1 = Compare Register 2/1 (= 5) 0 0 0 0 1 2 3 4 5 0 1 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
52
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., VDD). Voltages are given relative to VSS Parameters Supply voltage Input voltage (on any pin) Output short circuit duration Operating temperature range Storage temperature range Thermal resistance (SSO20) Soldering temperature (t 10 s) Symbol VDD VIN tshort Tamb Tstg RthJA Tsld Value -0.3 to +6.5 VSS -0.3 VIN VDD +0.3 Indefinite -40 to +85 -40 to +130 140 260 Unit V V s
C C
K/W
C
Operating Characteristics
VDD = 5 V, VSS = 0 V, Tamb = -40 to 85C unless otherwise specified
Parameters Power supply Active current CPU active Rext = 47 kW fSYSCL = fRCext /2 fSYSCL = fRCext /4 Rext = 47 kW fSYSCL = fRCext /2 fSYSCL = fRCext /4 fSYSCL = fRCext /16 VDD = 6.5 V IDD 330 170 40 35 30 0.5 370 190 45 40 35 0.8 A A A A A A Test Conditions Symbol Min. Typ. Max. Unit
Power down current (CPU sleep, RC-oscillator active) Sleep current (CPU sleep, RC-oscillator inactive)
IPD
ISleep
VDD = 5.5 V, VSS = 0 V, Tamb = -40 to +85C unless otherwise specified.
Parameters Active current CPU active Test Conditions Rext = 47 kW fSYSCL = fRCext/2 fSYSCL = fRCext/4 Rext = 47 kW fSYSCL = fRCext/2 fSYSCL = fRCext/4 fSYSCL = fRCext/16 Symbol IDD Min. Typ. 370 190 45 40 35 Max. 410 210 50 45 40 Unit A A A A A
Power down current (CPU sleep, RC oscillator active)
IPD
53
4708C-4BMCU-02/04
VSS = 0 V, Tamb = 25C unless otherwise specified.
Parameters Power-on Reset Threshold Voltage POR threshold voltage POR threshold voltage POR hysteresis Voltage Monitor Threshold Voltage VM high threshold voltage VM high threshold voltage VM low threshold voltage VM low threshold voltage External Input Voltage VMI VMI VMI > VBG, VMS = 1 VMI < VBG, VMS = 0 VVMI VVMI 1.1 1.25 1.25 1.4 V V VDD > VM, VMS = 1 VDD < VM, VMS = 0 VDD > VM, VMS = 1 VDD < VM, VMS = 0 VMThh VMThh VMThl VMThl 3.5 4.5 5.0 5.0 4.0 4.0 4.5 5.5 V V V V BOT = 1 BOT = 0 VPOR VPOR VPOR 2.5 3.5 3.0 4.0 50 3.5 4.5 V V mV Test Conditions Symbol Min. Typ. Max. Unit
All Bi-directional Ports
VSS = 0 V, Tamb = -40C to +85C unless otherwise specified.
Parameters Input voltage LOW Input voltage HIGH Input LOW current (dynamic pull-up) Input HIGH current (dynamic pull-down) Input LOW current (static pull-up) Input LOW current (static pull-down) Output LOW current Test Conditions VDD = 3.5 V to 6.5 V VDD = 3.5V to 6.5 V VDD = 3.5 V, VIL= VSS VDD = 6.5 V VDD = 3.5 V, VIH = VDD VDD = 6.5 V VDD = 3.5 V, VIL= VSS VDD = 6.5 V VDD = 3.5 V, VIH= VDD VDD = 6.5 V VOL = 0.2 VDD VDD = 3.5 V, VDD = 6.5 V VOH = 0.8 VDD VDD = 3.5 V, VDD = 6.5 V Symbol VIL VIH IIL IIH IIL IIH IOL Min. VSS 0.8 VDD -15 -50 15 50 -120 -300 120 300 3 8 -3 -8 -30 -100 30 100 -250 -600 250 600 5 15 -5 -16 Typ. Max. 0.2 VDD VDD -50 -200 50 200 -500 -1200 500 1200 8 22 -8 -24 Unit V V A A A A A A A A mA mA mA mA
Output HIGH current Note:
IOH
The pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller:
54
ATA6020N
4708C-4BMCU-02/04
ATA6020N
AC Characteristics
Operation Cycle Time
VSS = 0 V
Parameters System clock cycle Test Conditions VDD = 2.5 V to 6.5 V Tamb = -40C to +85C Symbol tSYSCL Min. 0.25 Typ. Max. 100 Unit s
Supply voltage VDD = 2.5 V to 6.5 V, VSS = 0 V, Tamb = 25C unless otherwise specified.
Parameters Timer 2 Input Timing Pin T2I Timer 2 input clock Timer 2 input LOW time Timer 2 input HIGH time Interrupt Request Input Timing Interrupt request LOW time Interrupt request HIGH time External System Clock EXSCL at OSC1 input EXSCL at OSC1 input Input HIGH time Reset Timing Power-on reset time RC-oscillator 1 Frequency Stability Stabilization time Frequency Stability Stabilization time External resistor VDD = 3.5V to 5.5 V Tamb = -40C to +85C VDD = 3.5 V to 5.5 V Rext = 47 kW VDD = 3.5 V to 5.5 V Tamb = -40C to +85C VDD = 3.5 V to 5.5 V fRcOut1
Df/f
Test Conditions
Symbol fT2I
Min.
Typ.
Max. 5
Unit MHz ns ns ns ns
Rise/fall time < 10 ns Rise/fall time < 10 ns Rise/fall time < 10 ns Rise/fall time < 10 ns ECM = EN Rise/fall time < 10 ns ECM = DI Rise/fall time < 10 ns Rise/fall time < 10 ns VDD >VPOR
tT2IL tT2IH tIRL tIRH
100 100 100 100
fEXSCL fEXSCL tIH tPOR
0.5 0.02 0.1 1.5 4
8 8
MHz MHz s
5
ms MHz
50 1 1.6 10 1 12 47 100
% ms MHz % ms kW
tS fRcOut2
Df/f
RC-oscillator 2 - External Resistor
tS Rext
55
4708C-4BMCU-02/04
Figure 55. Active Supply Current versus Frequency
2.000 1.800 1.600 Tamb = 25C VDD = 6.5 V 5V
IDDact (mA)
1.400 1.200 1.000 0.800 0.600 0.400 0.200 0.000 0 500 1000 1500 2000 2500 3000 3500
3V 2V
4000
System Clock (kHz)
Figure 56. Power-down Supply Current versus Frequency
250 Tamb = 25C 200 VDD = 6.5 V
IPD (A)
150
5V
4V 100 3V 50 2V
0 200
400
600
800
1000
1200
1400
1600
1800
2000
System Clock (kHz)
Figure 57. Active Supply Current versus VDD
0.600 fSYSCLK = 1 MHz 0.500
Tamb = 85C
IDDact (mA)
0.400
0.300
25C -40C
0.200
0.100
0.000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD (V)
56
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Figure 58. Power-down Supply Current versus VDD
90.0 80.0 70.0 60.0 fSYSCL = 500 kHz Tamb = 25C
IPD (A)
50.0 40.0 30.0 20.0 10.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD (V)
Figure 59. Internal RC Frequency versus VDD
5.60 5.40 5.20 5.00 4.80 4.60 4.40 4.20 4.00 3.80 3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2.00 2.0 2.5 3.0 3.5
fRC_INT (MHz)
Tamb = -40C
85C 25C
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
Figure 60. External RC Frequency versus VDD
1.730 1.710 Rext = 43k Tamb = -40C
fRC_EXT (MHz)
1.690 1.670 1.650 1.630 1.610 1.590 1.570 2.0 85C
25C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
57
4708C-4BMCU-02/04
Figure 61. Maximum System Clock versus VDD
12.00
fSYSCLK (MHz)
10.00
8.00
6.00
4.00
2.00
0.00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD (V)
Figure 62. Internal RC Frequency versus Tamb
5.60 5.40 5.20 5.00 4.80 4.60 4.40 4.20 4.00 3.80 3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2.00 -40 -30 -20 -10 0 10 20
fRC_INT (MHz)
VDD = 6.5 V
2V 3V
30
40
50
60
70
80
90
Tamb (C)
Figure 63. External RC Frequency versus Tamb
1.730 1.710 Rext = 43k
fRC_EXT (MHz)
1.690 VDD = 6.5 V 1.670 1.650 3V 1.630 1.610 1.590 1.570 -40 2V
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Tamb (C)
58
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Figure 64. External RC Frequency versus Rext
5500 VDD = 5 V 4500 Tamb = 25C
fRC_EXT (kHz)
3500
2500
max
typ.
1500
min
500 10 20 30 40 50 60 70 80 90 100 110
Rext (k)
Figure 65. Pull-up Resistor versus VDD
1000.0
VIL = VSS
Tamb = 85C
25C
RPU (k)
100.0
-40C
10.0 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
Figure 66. Strong Pull-up Resistor versus VDD
100.0 VIL = VSS
RSPU (k)
Tamb = 85C 25C
-40C 10.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD (V)
59
4708C-4BMCU-02/04
Figure 67. Output High Current versus VDD - Output High Voltage
0.0
VDD = 2.0 V
-5.0 -10.0 -15.0
3.0 V
IOH (mA)
4.0 V
-20.0 -25.0
Tamb = 25C 5.0 V
-30.0 -35.0 -40.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
6.5 V
VDD - VOH (V)
Figure 68. Pull-down Resistor versus VDD
1000 VIH = VDD
RPD (k)
Tamb = 85C 100 -40C
25C
10 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
Figure 69. Strong Pull-down Resistor versus VDD
100.0
VIH = VDD
RSPD (k)
Tamb = 85C
25C
-40C 10.0 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
60
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Figure 70. Output Low Current versus Output Low Voltage
30 Tamb = 25C 25 5V VDD = 6.5 V
IOL (mA)
20
15
4V
10
3V
5
2V
0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VOL (V)
Figure 71. Output High Current versus Tamb = 25C, VDD = 6.5 V, VOH = 0.8 VDD
0
-5
min.
-10
IOH (mA)
typ.
-15
max.
-20
-25 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Tamb (C)
Figure 72. Output Low Current versus Tamb, VDD = 6.5 V, VOL = 0.2 VDD
25
20
max.
15
typ.
IOL (mA)
10
min.
5
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Tamb (C)
61
4708C-4BMCU-02/04
Emulation
The basic function of emulation is to test and evaluate the customer's program and hardware in real time. This therefore enables the analysis of any timing, hardware or software problem. For emulation purposes, all MARC4 controllers include a special emulation mode. In this mode, the internal CPU core is inactive and the I/O buses are available via Port 0 and Port 1 to allow an external access to the on-chip peripherals. The MARC4 emulator uses this mode to control the peripherals of any MARC4 controller (target chip) and emulates the lost ports for the application. The MARC4 emulator can stop and restart a program at specified points during execution, making it possible for the applications engineer to view the memory contents and those of various registers during program execution. The designer also gains the ability to analyze the executed instruction sequences and all the I/O activities.
Figure 73. MARC4 Emulation
MARC4 emulator Program memory MARC4 emulation-CPU
I/O bus
Emulator target board
MARC4 target chip
Port 0
I/O control
Port 1
Trace memory
CORE
CORE (inactive) Peripherals
Port 0 Control logic
Port 1
Emulation control
SYSCL/ TCL, TE, NRST Application-specific hardware
Personal computer
62
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Option Settings for Ordering
Please select the option settings from the list below and insert ROM CRC.
Output Port 2 BP20 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] BP21 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] Port 4 BP40 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] BP41 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] BP42 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] BP43 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] [ ] Pull-up [ ] Pull-down [ ] Pull-up static [ ] Pull-down static [ ] Pull-up [ ] Pull-down [ ] Pull-up static [ ] Pull-down static [ ] Pull-up [ ] Pull-down [ ] Pull-up static [ ] Pull-down static [ ] Pull-up [ ] Pull-down [ ] Pull-up static [ ] Pull-down static Watchdog [ ] Softlock [ ] Hardlock Used oscillator [ ] Ext. RC [ ] Ext. clock ECM (External Clock Monitor) [ ] Enable [ ] Disable BP53 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] [ ] Pull-up [ ] Pull-down [ ] Pull-up static Pull-down static [ ] Pull-up [ ] Pull-down [ ] Pull-up static [ ] Pull-down static BP52 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] BP51 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] Input Port 5 BP50 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] [ ] Pull-up [ ] Pull-down [ ] Pull-up static [ ] Pull-down static [ ] Pull-up [ ] Pull-down [ ] Pull-up static [ ] Pull-down static [ ] Pull-up [ ] Pull-down [ ] Pull-up static [ ] Pull-down static [ ] Pull-up [ ] Pull-down [ ] Pull-up static [ ] Pull-down static Output Input
Please attach this page to the approval form.
Date: ____________
Signature: _________________________ Company: _________________________
63
4708C-4BMCU-02/04
Ordering Information
Extended Type Number(1) ATA6020x-yyy-TKQ ATA6020x-yyy-TKS Note: Program Memory 2 kB ROM 2 kB ROM Data-EEPROM No No Package SSO20 SSO20 Delivery Taped and reeled Tubes
1. x = Hardware revision yyy = Customer specific ROM-version
Package Information
Package SSO20
Dimensions in mm
6.75 6.50 5.7 5.3 4.5 4.3
1.30 0.25 0.65 5.85 20 11 0.15 0.05 0.15 6.6 6.3
technical drawings according to DIN specifications
1
10
64
ATA6020N
4708C-4BMCU-02/04
ATA6020N
Revision History
Changes from Rev. 4708A - 06/03 to Rev. 4708B - 12/03
Please note that the referring page numbers in this section are referred to the specific revision mentioned, not to this document. 1. Put datasheet in a new template. 2. Figure 5 "RAM MAP" on page 4 changed. 3. Table 9 "Peripheral Addresses" on page 19 changed. 4. New heading rows at Table "Absolute Maximum Ratings" on page 53 added. 5. Section "Emulation" on page 56 added. 6. Table "Ordering Information" on page 58 added. 7. Table name on page 57 changed.
Changes from Rev. 4708B - 12/03 to Rev. 4708C - 02/04
1. Figure 4 "ROM MAP" on page 4 changed. 2. Figure 55 to Figure 72 on page 56 to page 61 added.
65
4708C-4BMCU-02/04
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
(c) Atmel Corporation 2004. All rights reserved. Atmel (R) and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper.
4708C-4BMCU-02/04

▲Up To Search▲

Price & Availability of ATA6020N

	To Download ATA6020N Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .